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---Invensys Foxboro:

I/A Series system, FBM(input / output modules) Sequence control, ladder logic control, Recalling accident treatment, The digital-to-analog converter input/output signal processing, Data munication and processing, and etc.

---Invensys Triconex:

Redundancy fault tolerant control system, Based on the three module redundancy (TMR) structure of the most modern fault-tolerant

ABB信号处理器FSK160A 3BSE009514R1应用数字DSP工控备件数字信号处理器从20世纪70年代的专用信号处理器开始发展到VLSI阵列处理器，其应用领域已经从最初的语音、声纳等低频信号的处理发展到雷达、图像等视频大数据量的信号处理。由于浮点运算和并行处理技术的利用，信号处理器处理能力已得到***的提高。数字信号处理器还将继续沿着提高处理速度和运算精度两个方向发展在体系结构上数据流结构以至人工神经网络结构等将可能成为下一代数字信号处理器的基本结构模式。ABB信号处理器FSK160A 3BSE009514R1应用数字DSP工控备件算法格式DSP的算法有多种。绝大多数的DSP处理器使用***算法，数字表示为整数或-1.0到+1.0之间的小数形式。有些处理器采用浮点算法，数据表示成尾数加指数的形式：尾数×2指数。浮点算法是一种较复杂的常规算法，利用浮点数据可以实现大的数据动态范围。这个动态范围可以用和最小数的比值来表示。浮点DSP在应用中，设计工程师不用关心动态范围和精度一类的问题。浮点DSP比***DSP更容易编程，但是成本和功耗高。由于成本和功耗的原因，一般批量产品选用***DSP。编程和算法设计人员通过分析或仿真来确定所需要的动态范围和精度。如果要求易于开发，而且动态范围很宽、精度很高，可以考虑采用浮点DSP。ABB信号处理器FSK160A 3BSE009514R1应用数字DSP工控备件也可以在采用***DSP的条件下由软件实现浮点计算，但是这样的软件程序会占用大量处理器时间，因而很少使用。***办法是“块浮点”，利用该方法将具有相同指数，而尾数不同的一组数据作为数据块进行处理。“块浮点”处理通常用软件来实现。

The PFSK160A 3BSE009514R1 word width of all floating point DSP is 32 bits, while that of fixed point DSP is generally 16 bits. There are also 24 bit and 20 bit DSP, such as Motorola&＃39;s DSP563XX series and Zoran&＃39;s ZR3800X series. Since the word width has a great relationship with the external size of DSP, the number of pins and the size of memory required, the word width directly affects the cost of devices. The wider the word width is, the larger the size is. The more pins are, the larger the memory requirements are, and the cost increases accordingly. Under the condition of meeting the design requirements, DSP with small word width should be selected as far as possible to reduce the cost.When selecting fixed point and floating point, you can balance the relationship between word width and development complexity. For example, a 16 bit word width DSP device can also implement a 32-bit word width double precision algorithm by combining instructions. This method is also feasible if single precision can meet most computing requirements, while only a few codes require double precision. However, if most computing requirements require high precision, processors with large word width should be selected.Please note that the width of the instruction word and data word of most DSP devices is the same, but there are also some differences. For example, PFSK160A 3BSE009514R1the data word of ADSP-21XX series of ADI is 16 bits and the instruction word is 24 bits.Whether the processor meets the design requirements depends on whether it meets the speed requirements. There are many ways to test the speed of the processor, the most basic is to measure the instruction cycle of the processor.However, the instruction execution time does not indicate the real performance of the processor. Different processors can complete different tasks in a single instruction. Simply comparing the instruction execution time cannot just distinguish the difference in performance. Some new DSPs use a very long instruction word (VLIW) architecture. In this architecture,PFSK160A 3BSE009514R1 multiple instructions can be implemented in a single cycle time, PFSK160A 3BSE009514R1and each instruction performs fewer tasks than traditional DSPs. Therefore, compared with VLIW and general DSP devices, comparing the size of MIPS can be misleading.